1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. 40v, low quiescent current, 50ma linear regulator ISL80136 the ISL80136 is a high voltage, low quiescent current linear regulator ideally suited for ?always-on? and ?keep alive? applications. the ISL80136 operat es from an input voltage of +6v to +40v under normal operat ing conditions consuming only 18a of quiescent current at no load. the ISL80136 offers adjustable output voltages from 2.5v to 12v. it features an en pin that can be used to put the device into a low-quiescent current shutdown mode where it draws only 1.8a of supply current. the device features over-temperature shutdown and current limit protection. the ISL80136 is rated over the -40c to +125c temperature range and is available in an 8 lead epsoic with exposed pad package. features ? wide vin range of 6v to 40v ? adjustable output volt age from 2.5v to 12v ? guaranteed 50ma output current ? ultra low 18a typical quiescent current ? low 1.8a of typical shutdown current ? 1% accurate voltage reference ? low dropout voltage of 120mv at 50ma ? 40v tolerant logic level (ttl/cmos) enable input ? stable operation with 10f output capacitor ? 5kv esd hbm rated ? thermal shutdown and current limit protection applications ?industrial ?networking ? telecom related literature ? see fn7969 , ?isl80138 40v, low quiescent current, 150ma linear regulator? table 1. key differences in family of 40v ldo parts part number min. i out adj or fixed v out ISL80136 50ma adj isl80138 150ma adj figure 1. typical application figure 2. quie scent current vs load current (at unity gain), v in = 14v in out en adj gnd c in 0.1f c out 10f r1 r2 pad (gnd) 0 10 20 30 40 50 60 70 -50 0 50 100 150 temperature (c) quiescent current (a) load = 50ma load = 0ma december 15, 2011 fn7970.0 www.datasheet.co.kr datasheet pdf - http://www..net/
ISL80136 2 fn7970.0 december 15, 2011 block diagram pin configuration ISL80136 (8 ld epsoic) top view reference + soft-start control logic thermal sensor + - ea vin en gnd vout fet driver with current limit adj in nc nc en 1 2 3 4 8 7 6 5 out adj nc gnd pad (gnd) pin descriptions pin number pin name description 1 in input voltage pin. a minimum 0.1f x5r/x7r capacitor is required for proper operation. range: 6v to 40v 2, 3, 6 nc pins have internal termination and can be le ft not connected. connection to ground is optional. 4 en high on this pin enables the device. range: 0v to v in 5 gnd ground pin. 7 adj this pin is connected to the external feedback resistor divider, which sets the ldo output voltage.range: 0v to 3v 8 out regulated output voltage. a 10f x5r/x7r output capacitor is required for stability. range: 0v to 12v pad it is recommended to solder the pad to the ground plane. ordering information part number (notes 1, 2, 3) part marking temp. range (c) enable pin output voltage (v) package (pb-free) pkg. dwg. # ISL80136ibeajz 80136 ibeajz -40 to +125 yes adj 8 ld epsoic m8.15b ISL80136eval1z evaluation platform notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL80136 . for more information on msl please see techbrief tb363 . www.datasheet.co.kr datasheet pdf - http://www..net/
ISL80136 3 fn7970.0 december 15, 2011 absolute maximum rating s thermal information in pin to gnd voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +45v out pin to gnd voltage . . . . . . . . . . . . . . . . . . . . . . . . .. . .gnd - 0.3v to 16v en pin to gnd voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .gnd - 0.3v to in adj pin to gnd voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to3v output short-circuit duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . indefinite esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 5kv machine model (tested per jesd-a115-a) . . . . . . . . . . . . . . . . . . . 200v charge device model (tested per jesd22-c101c). . . . . . . . . . . . . 2.2kv latch up (tested per jesd78b; class ii, level a) . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 8 ld epsoic package (notes 4, 5). . . . . . . . 50 9 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +175c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . . . . . -40c to +125c in pin to gnd voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6v to +40v out pin to gnd voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+2.5v to +12v en pin to gnd voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0v to +40v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions , unless otherwise noted. v in = 14v, i out = 1ma, c in = 0.1 f, c out =10 f, t a = t j = -40c to +125c, unless otherwise noted. typical specifications are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +125c. parameter symbol test conditions min (note 8) typ max (note 8) unit input voltage range v in 640 v guaranteed output current i out v in = v out + vdo 50 ma adj reference voltage v ref en = high, v in = 14v, i out = 0.1ma 1.211 1.223 1.235 v line regulation v out / v in 3v v in 40v, i out = 1ma 0.04 0.115 % load regulation v out / i out v in = v out +v d, i out = 100a to 50ma 0.25 0.5 % dropout voltage (note 6) v do i out = 1ma, v out = 3.3v 10 38 mv i out = 50ma, v out = 3.3v 130 340 mv i out = 1ma, v out = 5v 10 48 mv i out = 50ma, v out = 5v 120 350 mv shutdown current i shdn en = low 1.8 3.64 a quiescent current iq en = high, i out = 0ma 18 24 a en = high, i out = 1ma 22 42 a en = high, i out = 10ma 34 60 a en = high, i out = 50ma 56 82 a power supply rejection ratio psr r f = 100hz; vin_ripple = 500mv p-p ; load = 50ma 58 db en function en threshold voltage v en_h v out = off to on 1.485 v v en_l v out = on to off 0.935 v en pin current i en v out = 0v 0.026 a en to regulation time (note 7) t en 1.65 1.93 ms protection features output current limit i limit v out = 0v 60 118 ma www.datasheet.co.kr datasheet pdf - http://www..net/
ISL80136 4 fn7970.0 december 15, 2011 thermal shutdown t shdn junction temperature rising +165 c thermal shutdown hysteresis t hyst +20 c notes: 6. dropout voltage is defined as (v in - v out ) when v out is 2% below the value of v out when v in = v out + 3v. 7. enable to regulation is the time the output takes to reach 95% of its final value with v in = 14v and en is taken from v il to v ih in 5ns. the output voltage is set at 5v. 8. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications recommended operating conditions , unless otherwise noted. v in = 14v, i out = 1ma, c in = 0.1 f, c out =10 f, t a = t j = -40c to +125c, unless otherwise noted. typical specifications are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min (note 8) typ max (note 8) unit www.datasheet.co.kr datasheet pdf - http://www..net/
ISL80136 5 fn7970.0 december 15, 2011 typical performance curves v in = 14v, i out = 1ma, v out = 5v, t j = +25 c unless otherwise specified. figure 3. quiescent current vs load current figure 4. quiescent cu rrent vs input voltage (no load) figure 5. shutdown current vs temp erature (en = 0) figure 6. output voltage vs temperature (load = 50ma) figure 7. output voltage vs load current figure 8. start-up waveform 0 10 20 30 40 50 60 70 80 0 1020304050 load current (ma) quiescent current (a) -40c +25c +125c quiescent current (a) 0 5 10 15 20 25 30 010203040 input voltage (v) -40c +25c +125c 0 0.5 1.0 1.5 2.0 2.5 3.0 -50 0 50 100 150 temperature (c) v in = 40v v in = 14v shutdown current (a) -0.010 -0.005 0 0.005 0.010 -50 0 50 100 150 v out = 5v v out =3.3v temperature (c) % output voltage variation 4.900 4.925 4.950 4.975 5.000 5.025 5.050 5.075 5.100 01020304050 load current (ma) -40c +25c +125c output voltage (v) en @ 500mv/div v out @ 1v/div time @ 500s/div www.datasheet.co.kr datasheet pdf - http://www..net/
ISL80136 6 fn7970.0 december 15, 2011 figure 9. power supply rejection ratio (load = 50ma) figure 10. load transient response typical performance curves v in = 14v, i out = 1ma, v out = 5v, t j = +25 c unless otherwise specified. (continued) 0 30 40 50 60 70 100 1k 10k 100k 1m frequency (hz) psrr (db) 20 10 v out = 5v v out = 3.3v 50ma 0ma v out @ 100mv/div time @ 5ms/div i out www.datasheet.co.kr datasheet pdf - http://www..net/
ISL80136 7 fn7970.0 december 15, 2011 functional description functional overview the ISL80136 is a high performance, high voltage, low-dropout regulator (ldo) with 50ma sourcing capability. the part is rated to operate over the -40c to +125c temperature range. featuring ultra-low quiescent current, it makes an ideal choice for ?always-on? applications. it works well under a ?load dump condition? where the input voltage could rise up to 40v. the device also features curren t limit and thermal shutdown protection. enable control the ISL80136 features an enable pin. when it is pulled low, the ic goes to a shutdown mode. in this condition, the device draws less than 2a. driving the pin high turns the device on. for always on operation, the en pin can be tied directly to in. current limit protection the ISL80136 has internal current limit functionality to protect the regulator during fault conditions. during current limit, the output sources a fixed amount of current largely independent of the output voltage. if the short or overload is removed from v out , the output returns to normal voltage regulation mode. thermal fault protection in the event that the die temperature exceeds typically +165c, the output of the ldo will shut down until the die temperature cools down to typically +145c. the level of power dissipated, combined with the ambient temperature and the thermal impedance of the package, will determine if the junction temperature exceeds the thermal shutdown temperature. also see the section on ?power dissipation?. application information input and output capacitors for the output, a ceramic capacitor (x5r or x7r) with a capacitance of 10f is recommended for the ISL80136 to maintain stability. the ground connection of the output capacitor should be routed directly to the gnd pin of the device and also placed close to the ic. a minimum of 0.1f (x5r or x7r) is recommended at the input. output voltage setting the output voltage is programmed using an external resistor divider, as shown in figure 11. the output voltage is calculated using equation 1: power dissipation the junction temperature must not exceed the range specified in ?recommended operating conditions? on page 3. the power dissipation can be calculated using equation 2: the maximum allowable junction temperature, t j(max) and the maximum expected ambient temperature, t a(max) will determine the maximum allowable junction temperature rise ( t j ), as shown in equation 3: to calculate the maximum ambient operating temperature, use the junction-to-ambient thermal resistance ( ja ), as shown in equation 4: board layout recommendations a good pcb layout is important to achieve expected performance. consideration shou ld be taken when placing the components and routing the trace to minimize the ground impedance, and keep the parasiti c inductance low. the input and output capacitors should have a good ground connection and be placed as close to the ic as possible. the adj feedback trace should be away from other noisy traces. connect the exposed pad to the ground plane for better heat dissipation. thermal vias on the pad increases heat dissipation. in out en (ISL80136) adj gnd c in 0.1f c out 10f r1 r2 figure 11. setting output voltage v out 1.223v r 1 r 2 ------ - 1 + ?? ?? ?? = (eq. 1) p d v in v out ? () i out v in i gnd + = (eq. 2) t j t jmax () t amax () ? = (eq. 3) t jmax () p dmax () x ja t a + = (eq. 4) www.datasheet.co.kr datasheet pdf - http://www..net/
ISL80136 8 fn7970.0 december 15, 2011 products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: ISL80136 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change december 15, 2011 fn7970.0 initial release. www.datasheet.co.kr datasheet pdf - http://www..net/
ISL80136 9 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7970.0 december 15, 2011 for additional products, see www.intersil.com/product_tree small outline exposed pad plastic packages (epsoic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m p1 123 p bottom view n top view side view m8.15b 8 lead narrow body small outline exposed pad plastic package symbol inches millimeters notes min max min max a 0.056 0.066 1.43 1.68 - a1 0.001 0.005 0.03 0.13 - b 0.0138 0.0192 0.35 0.49 9 c 0.0075 0.0098 0.19 0.25 - d 0.189 0.196 4.80 4.98 3 e 0.150 0.157 3.81 3.99 4 e 0.050 bsc 1.27 bsc - h 0.230 0.244 5.84 6.20 - h 0.010 0.016 0.25 0.41 5 l 0.016 0.035 0.41 0.89 6 n8 87 0 8 0 8 - p - 0.094 - 2.387 11 p1 - 0.094 - 2.387 11 rev. 5 8/10 notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional . if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: inch. c onverted millimeter dimensions are not necessarily exact. 11. dimensions ?p? and ?p1? are t hermal and/or electrical enhanced variations. values shown are maximum size of exposed pad within lead count and body size. www.datasheet.co.kr datasheet pdf - http://www..net/
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